Adele Poloziouk
Education
University of California, Santa Cruz Santa Cruz, CA
Bachelor of Science in Computer Engineering - Digital Hardware
Sept. 2021 – June 2025
- GPA: 3.87
- Dean’s Honors List, Tau Beta Pi (engineering)
Experience
Logic Design Lab Tutor April 2025 — Present
Jack Baskin Engineering, UCSC – Santa Cruz, CA
- Help students with System Verilog labs, oscilloscopes, CAD tools, and programmable logic
Undergraduate Web Developer July 2023 — Present
Jack Baskin Engineering, UCSC – genomics.ucsc.edu
- Build and maintain UCSC websites using WordPress, Divi, HTML/CSS, and JavaScript
- Enhance accessibility with Siteimprove, ensuring WCAG compliance
- Designed and implemented over 100 pages across affiliated institutions
Computer Networks Student Grader Oct 2024 — March 2025
Jack Baskin Engineering, UCSC – Santa Cruz, CA
- Graded assignments and supported 150 students learning networks and computer architecture
- Topics: network models, switching, MAC, error control, and routing algorithms
Computer Architecture Student Grader Jan 2024 — March 2024
Jack Baskin Engineering, UCSC – Santa Cruz, CA
- Evaluated assignments and exams focused on the MIPS ISA and RISC paradigm, memory systems, single-cycle and multi-cycle pipelines, and parallel processing
Projects
Multi-Polling Sensor | Python
- Built Raspberry Pi-based sensor hub using I2C to collect environmental data
- Logged data asynchronously with Python’s
asyncio
for optimized sensor polling
Morse Code LED Interpreter | C and Python
- Developed a Morse code transmission system using Python and C on Raspberry Pi 4, controlling an LED via GPIO.
- Programmed an ESP32-C3 to read photodiode signals through its ADC and decode Morse code in real time.
- Established synchronized I2C communication between Raspberry Pi and ESP32-C3 for reliable data exchange.
Toaster Oven | C | Demo
- Programmed a simulated toaster oven on a PIC32 (MIPS4K)microcontroller, using ADC input to control temperature and time via a physical dial.
- Demonstrated interrupt-driven control logic, timer configuration, and peripheral management in embedded C.
Chromatic Tuner | System Verilog
- Developed a real-time chromatic tuner on FPGA, leveraging RTL design principles to process live audio signals
- Implemented audio sampling modules and timing-accurate logic for precise frequency analysis and note detection
- Engineered sinusoid generation using Look-Up Tables (LUTs) to optimize resource utilization and accuracy in tone matching.
- Applied Digital Signal Processing (DSP) techniques, including FFT for frequency domain transformation and MAC (Multiply-Accumulate) operations for dominant frequency identification.
CDC FIFO | System Verilog
- Designed a clock domain crossing (CDC) FIFO to enable reliable data transfer between asynchronous clock domains.
- Implemented Gray code counters for robust and metastable read/write pointer synchronization.
- Integrated a ready/valid handshake interface and developed both asynchronous and synchronous RAM modules.
Osmosis Game | Verilog | Demo
- VGA game playable by using a Basys 3 Artix-7 FPGA Trainer Board
Skills
Languages:
Python, JavaScript, C/C++, Verilog, System Verilog, Assembly (RISC-V), HTML/CSS
Developer Tools/Skills:
Git, VS Code, Linux, Magic VLSI, LTSpice, Vivado, TCP/IP, HTTP, VirtualBox, MPLAB, MATLAB, WordPress, Excel, Oscilloscopes
Course Work:
Data Structures and Algorithms, Computer Systems and Assembly, C Programming, Python, Electric Circuits, Logic Design with Verilog, Computer Networks, Architecture, VLSI, Embedded System Design